Intel engineers have submitted a proposal for DRM Fabric, a vendor-neutral infrastructure designed to handle scale-up interconnects between GPUs and AI accelerators in Linux systems.
The timing is notable: the proposal arrived just days after AMD posted its UALink patch series for Linux, another effort focused on GPU interconnect technology.
Core Architecture
DRM Fabric aims to provide a protocol-agnostic topology layer for managing connections between accelerators, with an architecture built around four core concepts: fabric, endpoint, port, and peer. A fabric groups endpoints belonging to one provider-defined interconnect instance. An endpoint represents a single accelerator attachment with its physical ports. Each port reports lane capability, operational state, and optional counters. A peer identifies a directly adjacent accelerator or switch port—not a reference to a live kernel object. Peers may reference accelerators managed by another operating system or opaque switches in different trust domains.
The infrastructure records direct adjacency only, leaving end-to-end reachability and switch forwarding to a separate fabric controller. Vendor drivers continue handling hardware discovery, firmware interaction, memory semantics, and hardware-carried data paths. DRM Fabric manages topology and control state for DRM-managed accelerators without creating network devices or owning routing, forwarding, transport, or congestion control.
Netlink Considerations
The proposal favors Generic Netlink over sysfs or Devlink for this use case. According to the RFC, Generic Netlink maps better onto the multi-object, event-driven model required, particularly for dump enumeration and asynchronous notifications. Devlink was considered but models devices and subordinate objects rather than a fabric spanning multiple DRM devices.
Implementation Context
The implementation appears influenced by AMD‘s existing work. Intel engineers referenced AMDGPU‘s xGMI implementation when shaping DRM Fabric’s provider API. This suggests the team examined AMD’s approach before designing their own vendor-neutral abstraction.
Development timelines point toward Intel‘s upcoming Crescent Island AI accelerators, expected in 2026. The current RFC remains an early-stage proposal and does not yet address data transport, switch policy, live migration, MMU programming, or production provider implementations.
Patch Structure
The patch series splits into two parts. Patches 1 through 6 form a complete, independently testable read-only milestone, allowing the read-only functionality to be merged while provisioning discussions continue. These patches enable userspace to query the live topology graph through a small in-kernel API. Patches 7 through 12 introduce privileged provisioning capabilities, letting userspace create and delete fabrics, attach orphan endpoints, request administrative state changes, and manage peer adjacency. Provider drivers handle the actual hardware programming.
The full proposal is available on the dri-devel mailing list for developers interested in reviewing or contributing to the infrastructure.